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用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD / FPGA achieve floating-point computation methods
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是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。,Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
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实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
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浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
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FPGA的PS2口接口程序，可识别PS2口键盘的输入-FPGA-PS2 port interface program to identify the mouth PS2 keyboard input
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this double floating point vhdl code
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Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was to generate complex models with a movable camera. We wanted to be able to render complex images that consisted of hundreds to thousands of triangles. W
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this a descr iption for the floating point for the WIMAX-this is a descr iption for the floating point for the WIMAX
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数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件
csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序
fpinv.exe --- 倒数计算浮点数表的程序
dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHD
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This documents describes a free single precision floating point unit. This
floating point unit can perform add, subtract, multiply, divide, integer to
floating point and floating point to integer conversion.-This documents describes a free sing
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16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
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Floating Point Multiplier in VHDL
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VHDL语言，有符号定点数转化为浮点数，Pavle Belanovic教授编写-Conversion from signed fixed-point to floating-point representation
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给出了16位浮点FFT的算法代码及相关资料-Given a 16-bit floating-point FFT algorithm code and related information
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这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
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floating point adder mul and sub in verilog code
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floating point multiplier in VHDL
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floating point adder/subtractor in VHDL
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VHDL Code for 8 bit Floating Point Multiplication
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Arithmetic and logic unit for floating point single precision addition/substruction, multiplication, division and square root.
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